Clock signals are used for a variety of purposes in digital circuits, both on board level systems and integrated circuit (IC) devices. An integrated circuit such as a programmable logic device (PLD) typically receives one or more external reference clock signals to generate one or more internal clock signals to operate internal digital circuits. In synchronous systems, global clock signals are used to synchronize various circuits across the board or IC device. For example, internal circuits could be clocked by a first clock signal at a first clock frequency, while input/output (I/O) circuits are clocked by a second clock signal at a second clock frequency. As the complexity of digital systems increases, clocking schemes continue to become more complicated.
While multiple clock generating circuits could be used to generate the multiple clock signals, clock generating circuits typically consume a large amount of chip or board space. Therefore, most systems use one clock generating circuit to generate a first clock signal called a reference clock signal, and a specialized circuit to derive other clock signals from the reference clock signal. For example, clock dividers are used to generate one or more clock signals of lower clock frequencies from the reference clock signal. Typically, clock dividers divide the frequency of the reference clock signal by an integer value. Conversely, clock multipliers are used to generate one or more clock signals of higher clock frequencies from the reference clock signal. Combining clock multipliers with clock dividers provides clock circuits which can generate one or more clock signals having frequencies that are fractional values of the frequency of the reference clock signal, commonly called frequency synthesis. For example, if the generated clock frequency is 7/5 of the reference clock frequency, then the two clock edges should be in concurrence every 7 cycles of the generated clock signal and every 5 cycles of the reference clock signal.
However, these internal clock signals must be carefully controlled to ensure proper timing in the integrated circuit. It is important for proper operation of the integrated circuit device that a generated clock signal be maintained accurately at the specified phase and frequency. This is often done by assuring that the phase of the generated clock signal coincides with that of the reference clock signal when concurrence should occur. Clock management circuits are used in integrated circuits to perform such functions as deskewing, shifting, as well as frequency synthesis. Traditionally, frequency synthesis is done using Phase-Locked Loops (PLLs) that control the phase and frequency by adjusting an analog voltage. Since using analog voltages increases the sensitivity to noise, fully-digital solutions are attractive for on-chip integration.
Delay-locked loops (DLLs) are also used to manage the propagation delay of the clock signals by using a delay line. If the delay line in the oscillator is voltage-controlled, analog circuits adjust the frequency by adjusting the voltage applied to the delay line (i.e. voltage-controlled delay elements). In an oscillator based on a tap-controlled delay (TCD) line, a number of delay elements in a delay line is used to control the frequency, where the number of the delay elements in a TCD is dictated by the lowest frequency range. A delay-locked loop can be used with a digital frequency synthesizer to maintain the phase between the input clock and the output clock generated by the digital frequency synthesizer.
Digital frequency synthesizers often have low and high frequency operating modes. These operating modes, which define both input and output frequency restrictions, must be selected by a user. In order for the digital frequency synthesizer to generate an output signal, the digital frequency synthesizer must lock on the reference signal. However, if the reference signal is not within the range of input signals selected by the user, the frequency synthesizer will not lock on reference signal and will not generate the desired synthesized clock signal. Further, a conventional tap-controlled delay line may be sensitive to environmental and operating conditions such as process variations, voltage, temperature, and noise. Tap-controlled delay lines can also occupy a large amount of area, and may introduce duty cycle distortion. Finally, conventional frequency synthesis circuits often require clocks in different clock domains to provide course and fine searching to lock to a reference clock.
Accordingly, there is a need for a method of and circuit for efficiently generating a clock signal in an integrated circuit.